Conductive lines are widely used for interconnections in integrated circuits. For example, conductive lines may be used to transmit data to and from a memory array within a Dynamic Random Access Memory (DRAM) integrated circuit. As the level of integration increases in integrated circuits so there may be a need to reduce the width of conductive lines such as bit lines. In particular, integrated circuits having a critical line width less than 0.3 .mu.m may be limited in the degree of integration. Accordingly, untapped bit lines have been widely used to further increase the degree of integration.
FIG. 1A to FIG. 1C illustrate methods of fabricating bit lines according to the prior art. As shown in FIG. 1A, an interlevel insulating layer 12 is formed on a conductive layer 11. The interlevel insulating layer 12 is etched to form a bit line contact hole 13. The bit line contact hole 13 is formed in the interlevel insulating layer 12 so as to expose a portion of the conductive layer 11.
As shown in FIG. 1B, a conductive material 14 is formed on the interlevel insulating layer 12, on the conductive layer 11 and in the bit line contact hole 13. A photoresist pattern 15 is then formed to provide patterning for the conductive material 14. The photoresist pattern 15 provides a window 16 that is about the same size as the bit line contact hole 13 so as to avoid the formation of taps on the bit line. However, a mask misalignment 15A may cause overetching of the conductive material 14 within the contact hole 16 and thereby increase the bit line resistance.
As shown in FIG. 1C, the portion of the conductive material 14 that lies outside the window 16 is removed via an etching process.
FIG. 2A to FIG. 2C illustrate methods of fabricating a bit line using a damascene process to address the problems associated with the above described mask misalignment according to the prior art.
As shown in FIG. 2A, an interlevel insulating layer 22 is formed on a conductive layer 21. The interlevel insulating layer 22 is etched to form a bit line contact hole 23. The bit line contact hole 23 exposes the conductive layer 21.
As shown in FIG. 2B, a conductive material 24 is formed on the interlevel insulating layer 22, on the conductive material 21 and in the bit line contact hole 23.
As shown in FIG. 2C, the bit line 24 is formed by a Chemical Mechanical Polishing (CMP) method. Accordingly, the portion of the conductive material 24 on the interlevel insulating layer 22 is removed. Finally, a capping layer may be formed on the interlevel insulating layer 22 and the bit line 24. In particular, a nitride layer may be used to cap the bit line by capping both the sidewalls and the top of the bit line using a self-aligned contact process so as to prevent a short between storage node contacts. It may however be difficult to cap both the sidewalls and the top of the bit line using the damascene process according to the prior art.